The present application claims priority under 35 U.S.C. xc2xa7119 to Korean Patent Application No. 2000-73802 filed on Dec. 6, 2000, which is hereby incorporated by reference in its entirety for all purposes.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a wordline driver for ensuring equal stress to wordlines in a multi row address disturb test and a method of driving the wordline driver.
2. Description of the Related Art
As the storage capacity of semiconductor memory devices increases, the time required to test semiconductor memory devices increases. To reduce the test time, particularly for a dynamic random access memory, a method of enabling a plurality of wordlines simultaneously is sometimes used instead of a method of enabling one wordline for the test. The process in which one wordline is enabled to sense a memory cell data is called a xe2x80x9cdisturbxe2x80x9d, and the process in which a plurality of wordlines are enabled to sense the data of a plurality of memory cells simultaneously, is called a multi-row address disturb (MRAD). Therefore, the MRAD mode is advantageous in reducing the time required to test a semiconductor memory device in comparison to the disturb mode.
The structure of a circuit enabling wordlines and the operation timing diagram thereof are illustrated in FIGS. 1 through 4. FIG. 1 is a diagram illustrating a conventional row address pre-decoder 100. The row address pre-decoder 100 combines externally input row addresses RA0 through RA11 and then generates address decoding signals DRA01 through DRA91011. The address decoding signal DRA01 is a signal made by combining the row addresses RA0 and RA1. The address decoding signal DRA234 is a signal made by combining the row addresses RA2, RA3, and RA4. The address decoding signals DRA56, is made by combining the row address signals RA5 and RA6, and the address decoding signals DRA78 is made by combining the row address signals RA7 and RA8. Finally, the address decoding signal DRA91011 is made by combining the row address signals RA9, RA10 and RA11.
FIG. 2 is a diagram illustrating a sub-wordline decoder 200. The sub-wordline decoder 200 generates sub-wordline signals PXi and PXiB through the combination of the address decoding signals DRA01 and DRA91011. As the sub-wordline decoder is driven by a boosting voltage Vpp, the voltage level of the sub wordline signals PXi and PXiB appears to be the boosting voltage Vpp.
FIG. 3 is a diagram illustrating a conventional wordline driver 300. The wordline driver 300 includes a main decoder 310 and a driver 320. The main decoder includes a PMOS transistor 311 that responds to a pre-charge signal PRECH; NMOS transistors 312, 313, 314 and 315 connected in series, that respond to the address decoding signals DRA234, DRA56, DRA78 and DRA91011, respectively; and an inverter 316 that responds to a node A placed between the PMOS transistor 311 and the first NMOS transistor 312. The output of the inverter 316 becomes a normal wordline enable signal NWEi. A driver 320 includes an NMOS transistor 321 which transmits the normal wordline enable signal NWEi to a node B in response to the boosting voltage Vpp, an NMOS transistor 322 which transmits the normal wordline enable signal NWEi to a wordline WLi in response to the sub-wordline signal PXi, an NMOS transistor 323 which transmits the sub-wordline signal PXi to the wordline WLi in response to the voltage of the node B, and an NMOS transistor 324 which discharges the wordline WLi to ground in response to the complementary sub-wordline signal PXiB.
The operation of the MRAD mode illustrated in FIGS. 1 through 3 will be described with reference to the timing diagram of FIG. 4. Referring to FIG. 4, a sub-wordline signal PXi and normal wordline enable signals NWE0, NWE1, NWE2 and so on are generated by receiving address signals ADDR in every row active command interval. The first normal wordline enable signal NWE0 generated in a first row active command interval P1 and the sub-wordline signal PXi generate a wordline WL0 and also selectively generate WL1 through WL3 (not shown). The second normal wordline enable signal NWE1 generated in a second row active command interval P2 and the sub-wordline signal PXi generate a wordline WL4 and selectively generate WL5 through WL7 (not shown). The third normal wordline enable signal NWE2 generated in a third row active command interval and the sub-wordline signal PXi generate a wordline WL8 and selectively generate wordlines WL9 through WL11 (not shown).
In the first row active command interval P1, the first normal wordline enable signal NWE0 of the boosting voltage Vpp is transmitted to the node B of FIG. 3, and subsequently the sub-wordline signal PXi is coupled to the node B by a gate-source capacitance of the NMOS transistor 323, known as a self-boosting phenomenon. Consequently, the node B has a voltage of 2 Vppxe2x88x92Vt and the first wordline WL0 is at the boosting voltage Vpp.
On the contrary, in the second row active command interval P2, the second normal wordline enable signal NWE1 is at the boosting voltage Vpp and the sub-wordline signal PXi is in an already enabled condition so as to be at the boosting voltage Vpp. Consequently, the node B is at the voltage level of Vppxe2x88x92Vt. Then, the fifth wordline WL4 is at the voltage level of Vppxe2x88x922 Vt. In the same way, the ninth wordline WL8 is at the voltage level of Vppxe2x88x922 Vt in the third row active command interval P3.
In other words, during the test in the MRAD mode, the voltage level of the first wordline WL0 is different from that of the subsequent wordlines including the fifth and ninth wordlines WL4 and WL8 and so on, because of the fact that the former is Vpp and the latter are Vppxe2x88x922 Vt. If an NMOS transistor is used as a cell transistor, a high voltage must be applied to the cell gate for the purpose of preventing loss of memory cell data. At this time, if the fifth and ninth wordlines WL4 and WL8 are set to be at the Vpp voltage, the first wordline WL0 is at the voltage level of Vpp+2 Vt. Consequently, the first wordline WL0 is over-stressed by 2 Vt compared to the fifth and ninth wordlines WL4 and WL8. Memory cells which are connected to the first wordline WL0 and which are consequently over-stressed, can cause reliability problems with respect to a gate oxide layer.
Therefore, a wordline driver which can prevent a firstly-enabled wordline in which a self-boosting phenomenon occurs from being over-stressed during a test in the MRAD mode, and a corresponding driving method, are needed to overcome such problems.
The present invention is therefore directed to a wordline driver, and method of driving the wordline driver, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an object of the present invention to provide a wordline driver which can apply equal stress to each wordline during a multi-row address disturb test in which a plurality of wordlines are sequentially enabled, so that an equal stress is applied to each of the wordlines.
It is another object of the present invention to provide a corresponding method of driving the wordline driver.
Accordingly, to achieve the first and other objects of the invention, there is provided a wordline driver including a control unit which generates decoder control signals from predetermined signals among externally input address decoding signals in response to signals of a multi-row address disturb (MRAD) mode in which a plurality of wordlines are sequentially enabled, a decoder which generates normal wordline enable signals in response to the address decoding signals and the decoder control signals, and a driver which drives sub-wordline signals generated by combining the address decoding signals as wordlines in response to the normal wordline enable signals. In the multi-row address disturb mode, the wordline enable signals are generated later than the sub-wordline signal.
The control unit may include a first transmitting unit which transmits the address decoding signals in response to the deactivation of the multi-row address disturb signals, a second transmitting unit which transmits the address decoding signals in response to the activation of the multi-row address disturb signals, a delay unit which receives the output of the second transmitting unit and delays it for a predetermined time, and a NOR gate which generates the decoder control signals in response to the output of the first transmitting unit and delay unit.
To achieve the second and other objects of the invention, there is provided a wordline-driving method including transmitting address decoding signals in response to the deactivation of multi row address disturb signals; transmitting the address decoding signals in response to the activation of the multi row address disturb signals; receiving an output of the second step and delaying it for a predetermined time; generating decoder control signals in response to an output of the third step; generating sub-wordline signals through the combination of the address decoding signals; generating normal wordline enable signals in response to the address decoding signals and the decoder control signals; and driving the sub-wordline signals as wordlines in response to the normal wordline enable signals.
According to the present invention, the voltage level of each of the wordlines enabled in the MRAD mode is almost the same as Vppxe2x88x922 t. Therefore, it is possible to prevent a wordline which is enabled first in a test performed in a conventional MRAD mode from being over-stressed due to self-boosting.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.